The invention relates to scan testing of digital circuitry, particularly in a concurrently running computer.
2. Background
A computer system which is able to continue operating even when faults occur in a subcomponent is highly desirable in a variety of situations. By way of example, a large corporation may have all its activities controlled by a central computer system. Such a corporation can ill afford to suffer complete system shutdown because of a fault in a minor subcomponent of the system. If one part of the computer system fails, other parts should continue to be available for productive operations. The failed part should be structured for quick fault isolation and repair so that it can be rapidly brought back on line after a failure. And to prevent unexpected failures from occurring in the first place, mechanisms should be provided in each part of the computer system for performing routine maintenance, error logging and fault elimination.
Scan testing subsystems are one type of mechanism by which otherwise difficult-to-access components within a complex system of computer or other digital circuits can be accessed and their states detected and altered to detect and/or correct functional errors. Examples of scan test structures and their uses may be found in the following U.S. Patents: (A) U.S. Pat. No. 4,244,019, DATA PROCESSING SYSTEM INCLUDING A PROGRAM-EXECUTING SECONDARY SYSTEM CONTROLLING A PROGRAM-EXECUTING PRIMARY SYSTEM, issued to Anderson et al, Jan. 6, 1981; (B) U.S. Pat. No. 4,752,907, INTEGRATED CIRCUIT SCANNING APPARATUS HAVING SCANNING DATA LINES FOR CONNECTING SELECTED DATA LOCATIONS TO AN I/O TERMINAL, issued to Si, et al. Jun. 21, 1988; and (C) U.S. Pat. No. 4,819,166, MULTI-MODE SCAN APPARATUS, issued to Si et al Apr. 4, 1989. U.S. Pat. No. 4,661,953, ERROR TRACKING APPARATUS IN A DATA PROCESSING SYSTEM, issued to Venkatesh et al, Apr. 28, 1987 discloses an error history logging method whose relevance to the present application will be seen below. The disclosures of these patents are incorporated here by reference.
A scan testing subsystem is typically formed by defining a set of uniquely addressable scan points (e.g., SP.sub.001, SP.sub.002, SP.sub.003, etc.) located at preselected parts inside of a system to be tested. The system to be tested (hereafter also System Under Test or SUT) typically includes one or more circuits whose internal nodes are not easily accessed. By way of example, each such circuit can be an integrated circuit (IC) chip which has been packaged such that direct connection to internal components of the IC chip is no longer possible. By way of further example, each such circuit can be mounted on a printed circuit board which has been conformably coated and/or inserted into a chassis such that it is no longer convenient to make direct connection to wires of the board for test purposes.
To access the internal nodes of such systems, scan point reading means are provided for uniquely addressing each scan point (hereafter, SP.sub.xyz, where "x" "y" and "z" are arbitrary identifiers) within the system under test (SUT). The reading means detects the state of an addressed scan point, SP.sub.xyz, and relays the detected state to a point external of the SUT so that the state of the addressed point can be studied.
If a scan point (SP.sub.xyz) is driven either directly or indirectly by a bistable latch, then scan point driving means are also provided for addressing that latch, forging it into a predetermined state (usually the logic high or "set" state ("1")) and thereby driving its corresponding scan point (SP.sub.xyz) into a responsive state. A latch which drives a scan point (SP.sub.xyz) either directly or indirectly is referred to here as a scan latch and denoted by SL.sub.xyz.
In a conventional scan testing procedure, every scan latch (SL.sub.xyz) in the system under test (SUT) is disabled from responding to signals presented at a normal data input terminal (D) of that latch. This is usually done by disabling a clock distribution line which supplies clock pulses to all the scan latches (SL.sub.xyz). The data output terminal (Q) of each scan latch (SL.sub.xyz) can be forced to a logic one state ("1"), even though the latch is not being clocked, by applying a logic "1" to a set terminal (SET) of the latch. The data output terminal (Q) can be forced to a logic zero state "0" by applying a logic "1" to an opposing reset terminal (RST) of the scan latch (SL.sub.xyz). The forced state propagates from the output terminal (Q) to a circuit of interest within the system under test (SUT) and the response of the circuit to such stimulus is detected at an appropriate scan point.
When the system under test (SUT) is a high density one which is implemented on a circuit supporting substrate of limited area, e.g., on the semiconductor substrate of an IC chip, then a single addressing circuit is preferably used to simultaneously identify each scan point (SP.sub.xyz) whose state is to be read and to identify each scan latch (SL.sub.xyz) whose state may have to be forced to a predetermined first state (usually the "1" state). This simultaneous addressing approach is taken to minimize the amount of circuitry used for the scan point reading and scan latch setting functions. The limited area of the circuit supporting substrate (e.g., IC chip substrate) is thereby conserved for implementing other functions.
Scan functions are used primarily for test purposes and only rarely to support normal circuit functions. Accordingly, from the view point of normal circuit functionality, the scan-implementing circuitry is considered undesirable overhead and the conventional philosophy is to implement the scan testing functions with as little circuitry as possible.
In keeping with this philosophy, no means is provided within a conventional scan subsystem for forcing each scan latch (SL.sub.xyz) individually into an opposed second state (i.e., the "0" state) after it has been addressed by the single addressing means and forced into the first state (the "1" state). Instead, a global reset line which connects to all the scan latches (SL.sub.xyz) is activated to simultaneously force them all into the second state ("0"). Then, those particular scan latches which need to be placed in the first state ("1") are individually addressed, one at a time, by the single addressing means and forced into the first state ("1").
Thus, all the scan latches are addressed in parallel as a unitary body when the state of one or more scan latches has to be switched from a logic "1" to a logic "0". Each scan latch is thereafter individually and serially addressed if its state is to be conversely switched from a logic "0" to a logic "1". Any combination of logic ones and zeroes (1's and 0's) can be loaded into an array of scan latches with this technique. Each combination of 1's and 0's to-be-loaded into all the scan latches of a system under test (SUT) is referred to here as a complete test vector. A shorter sequence of 1's and 0's inside of a complete test vector is referred to here as a test vector subsequence.
A disadvantage of the above described technique comes to light when a single bit of an already-loaded and relatively-long (i.e. 100 bits long) test vector has to be changed from a logic "1" to a logic "0" while all other bits are to remain unchanged. Before a global reset command is issued, the state of the complete test vector has to be preserved by storing a copy of it in a random access memory (RAM) or other data storage device which is external to the system under test (SUT). If the system under test has one or more VLSI (Very-Large Scale Integration) chips and each VLSI chip has 512 or more scan latches defined within its circuitry then the 512 or more scan latches of each VLSl chip will have to be addressed, one at a time, to detect their current states and the detected states will have to be preserved in external RAM or some other data storage medium. The global reset line is thereafter activated to clear all the scan latches. The state of the one bit to be changed is toggled within the external RAM device. And the contents of the external RAM device are then reloaded into the scan latches of the SUT by addressing each scan latch (SL.sub.xyz) which is to contain a logic "1", one at a time, and forcing it into the "1" state through its SET terminal.
Given the high storage densities and high bit rates of modern logic circuits, it is not considered a problem to maintain a copy of some 512 bits in an external RAM (or a relatively low multiple of 512, such as 1024 or 2048 bits), to edit some of these bits and to shuffle all the bits back into the scan latches of a system under test (SUT) every time the complete test vector of the SUT has to be changed. But this assumes that the SUT comprises one or perhaps just a few VLSI chips. Some types of systems to be tested (SUT's) have hundreds of VLSI chips. A complete test vector for such SUT's may contain millions of bits and such SUT's may require thousands or millions of different test vectors to be applied to each chip all within a limited time span.
High-performance computers such as an IBM or Amdahl mainframe are examples of such test-intensive systems. Testing has to be performed in reasonable time and typically, a same pattern of test vectors has to be loaded repeatedly, many times during the life of the system. So the amount of time consumed by a too-slow test-vector loading procedure disadvantageously accumulates over the life of the computer.
One impediment to faster testing is the inherent delay in above-mentioned technique for changing the complete test vector within the SUT. The global reset command switches the states of all scan latches in one step. But thereafter, the scan latches are reloaded with logic "1's" one at a time using a serial addressing scheme. When the system under test (SUT) comprises many and/or a relatively complex set of VLSI chips, it can take an undesirably long time to serially load each bit of each test vector again and again into each scan latch after every global reset. It would be advantageous to have a mechanism whereby one could quickly change a test vector at a few points of interest inside a large machine without having to preserve the states of all the scan latches in an external RAM device and without having to reload all the scan latches of the machine just so that a slightly altered test vector can be tried.